Bring compute and data closer.
Compute chiplets, I/O chiplets, stacked SRAM and HBM4E form a scalable package that reduces data movement across boards.
HMGO SuPro 1 Series
Not a consumer processor made larger. SuPro 1 redesigns the complete system—from silicon, memory and optical fabric to compilers and recovery—for large-model training, scientific computing and giant servers.
Supercomputing, end to end
Compute chiplets, I/O chiplets, stacked SRAM and HBM4E form a scalable package that reduces data movement across boards.
HM-Mesh X1 carries the same collective communication, telemetry and recovery semantics across package, tray, rack and cluster.
From ECC and link replay to incremental checkpoints and elastic scheduling, long-running jobs can isolate a failure and keep moving.
Five processors. One architecture.
From an AI2 Ultra-class migration entry point to an extreme package and a next-generation development preview.
An accessible SuPro node for workstation code, quantised models and small clusters, using a conceptual compute level aligned with HMGO AI2 Ultra.
The standard supercomputing processor for research and enterprise AI, balancing large models, FP64 simulation and private departmental compute.
Six compute chiplets, dual fault domains and complete RAS for 10-trillion-parameter training, critical services and production runs lasting weeks.
Eight compute chiplets, four I/O chiplets and co-packaged optics form an extreme unit for frontier models, global climate simulation and digital twins.
A development preview of HM-Ark V7, Matrix Ocean Gen 5 and HM-Link X2 for early software, network, power and cooling validation.
SuPro 1 Ultra
In HMGO's internal HyperScale Transformer Throughput projection, SuPro 1 Ultra reaches up to 800× the projected throughput of a single Apple M5 Max system.
This figure assumes FP4 weights, FP8 activations, long-context batching and a server-class power envelope. It is a conceptual cross-category projection, not an independent third-party measurement, and does not represent every workload.
Read the performance methodology ↗Inside SuPro
64-bit HM-Ark V6 · multithreaded control and FP64 vectors
FP4 / FP8 / BF16 / TF32 / FP64 variable-precision matrix engines
Numerical parallelism, ray-traced visualisation and geometry reconstruction
Network, storage, encryption and distributed checkpoint offload
One optical fabric from the package to 65,536 nodes
Portfolio at a glance
| Model | FP4 concept peak | Memory | Bandwidth | Sustained power | Primary workloads |
|---|---|---|---|---|---|
| SuPro 1 Lite | 61.44 POPS | 2 TB HBM4 | 8 TB/s | 450 W | AI2 Ultra migration · small clusters |
| SuPro 1 | 0.42 EFLOPS | 4 TB HBM4E | 18 TB/s | 700 W | General HPC · research · enterprise AI |
| SuPro 1 Pro | 2.8 EFLOPS | 12 TB HBM4E | 64 TB/s | 1.8 kW | Large servers · model training |
| SuPro 1 Ultra | 12.8 EFLOPS | 48 TB HBM4E | 192 TB/s | 6 kW | Frontier models · global simulation |
| SuPro 2 Preview | 20.0 EFLOPS target | 64 TB HBM5-P | 256 TB/s | 5.5 kW | Next-generation development validation |
Technology Publications
Three complete technical publications, 36 pages in total, available to open or download.
Heterogeneous packaging, HBM4E, HM-Mesh X1, scale-out systems, RAS, security and the methodology behind the 800× projection.
Open PDF ↗Complete parameters for five models, including roles, memory, fabric, power, target workloads and platform qualification.
Open PDF ↗Rack power-up, the HM-Forge stack, distributed training, scientific computing, recovery, secure operations and acceptance checklists.
Open PDF ↗Concept disclosure
HMGO SuPro 1 is an original conceptual processor family. Process nodes, performance, power, interfaces, product plans and software names shown on this page and in its documents are design assumptions, not shipping hardware or third-party validated results. Apple and M5 Max are trademarks of their respective owners.